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| CDP1822C/3 March 1997 High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM Description The CDP1822C/3 is a 256 word by 4-bit random access memory designed for use in memory systems where high speed, low operating current, and simplicity in use are desirable. The CDP1822 features high speed and excellent noise immunity. It has separate data inputs and outputs and utilizes a single power supply of 4V to 6.5V. Two Chip Select inputs simplify system expansion. An output Disable control provides Wire-OR-capability and is also useful in common Input/Output systems. The Output Disable input allows this RAM to be used in common data Input/Output systems by forcing the output into a high impedance state during a write operation independent of the Chip Select input condition. The output assumes a high impedance state when the Output Disable is at high level or when the chip is deselected by CS1 and/or CS2. The high noise immunity of the CMOS technology is preserved in this design. For TTL interfacing at 5V operation, excellent system noise margin is preserved by using an external pull-up resistor at each input. Features * For Applications in Aerospace, Military, and Critical Industrial Equipment * Interfaces Directly with CDP1802 Microprocessor * Very Low Operating Current - At VDD = 5V and Cycle Time = 1s . . . . . . 4mA (Typ) * Static CMOS Silicon-On-Sapphire Circuitry - CD4000 Series Compatible * Industry Standard Pinout * Two Chip Select Inputs - Simple Memory Expansion * Memory Retention for Standby. . . . . . . . . . . . . 2V (Min) Battery Voltage * Single Power Supply Operation . . . . . . . . . . 4V to 6.5V * High Noise Immunity 30% of VDD. . . . . . . . . 4V to 6.5V * Output Disable for Common I/O Systems * Three-State Data Output for Bus Oriented Systems * Separate Data Inputs and Outputs * Latch-Up-Free Transient Radiation Tolerance Ordering Information PACKAGE SBDIP TEMP. RANGE -55oC to +125oC PART NUMBER CDP1822CD3 PKG. NO. D22.4A Pinout CDP1822C/3 (SBDIP) TOP VIEW A3 1 A2 2 A1 3 A0 4 A5 5 A6 6 A7 7 VSS 8 DI1 9 DO1 10 DI2 11 22 VDD 21 A4 20 R/W 19 CS1 18 O. D. 17 CS2 16 DO4 15 DI4 14 DO3 13 DI3 12 DO2 OPERATIONAL MODES INPUTS CHIP SELECT 1 (CS1) 0 0 0 1 X X CHIP SELECT 2 (CS2) 1 1 1 X 0 X OUTPUT READ/ DISABLE WRITE (OD) (R/W) 0 0 1 X X 1 1 0 0 X X X MODE Read Write Write Standby Standby Output Disable OUTPUT Read Data In High Impedance High Impedance High Impedance High Impedance Logic 1 = High, Logic 0 = Low, X = Don't Care CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 File Number 2981.1 6-19 CDP1822C/3 Absolute Maximum Ratings DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1822C/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Thermal Information Thermal Resistance (Typical) JA (oC/W) JC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . 80 21 Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Lead Temperature (During Soldering) . . . . . . . . . +265oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150oC Recommended Operating Conditions At TA = Full Package Temperature Range.For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS PARAMETER DC Operating Voltage Range Input Voltage Range MIN 4 VSS MAX 6.5 VDD UNITS V V Static Electrical Specifications CONDITIONS -55oC, +25oC PARAMETER Quiescent Device Current (Note 1) Output Low (Sink) Current (Note 1) Output High (Source) Current (Note 1) Output Voltage Low-Level Output Voltage High-Level Input Low Voltage SYMBOL IDD IOL IOH VOL VOH VIL VIH IIN IDD1 IOUT CIN COUT VO (V) 0.4 4.6 0.5, 4.5 VIN (V) 0, 5 0, 5 0, 5 0, 5 0, 5 VDD (V) 5 5 5 5 5 5 MIN 2.6 VDD - 0.1 MAX 390 -1.2 0.1 0.3 VDD 3.2 6.5 3.2 7.5 7.5 LIMITS +125oC MIN 1.6 VDD - 0.5 MAX 1000 -0.8 0.5 0.3 VDD 10 10 19 7.5 7.5 UNITS A mA mA V V V Input High Voltage Input Leakage Current (Note 1) Operating Current (Note 1) Three-State Output Leakage Current Input Capacitance Output Capacitance NOTE: 0.5, 4.5 0, 5 0, 5 0, 5 0, 5 5 5 5 5 0.7 VDD - 0.7 VDD - V A mA A pF pF - - - - - 1. Limits designate 100% testing, all other limits are designer's parameters under given test conditions and do not represent 100% testing. 6-20 CDP1822C/3 Read Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF LIMITS +25oC, -55oC PARAMETER Read Cycle (Note 1) Access from Address (Note 1) Output Valid from Chip Select 1 (Note 1) Output Valid from Chip Select 2 (Note 1) Output Active from Output Disable (Note 1) Output Hold from Chip Select 1 Output Hold from Chip Select 2 Output Hold from Output Disable NOTE: 1. Limits designate 100% testing. All other limits are designer's parameters under given test conditions and do not represent 100% testing VDD tRC A0 - A7 tADA READ ADDRESS DECODER VSS WRITE ADDRESS DECODER +125oC MIN 500 20 20 20 MAX 500 500 500 225 UNITS ns ns ns ns ns ns ns ns SYMBOL tRC tADA tDOA1 tDOA2 tDOA3 tDOH1 tDOH2 tDOH3 VDD (V) 5 5 5 5 5 5 5 5 MIN 370 10 10 10 MAX 370 370 370 170 - CHIP SELECT 1 tDOH1 tDOH2 CHIP SELECT 2 OUTPUT DISABLE tDOA2 (NOTE 1) tDOA3 (NOTE 1) tDOH3 READ/ WRITE DATA OUT DATA OUT VALID HIGH IMPEDANCE HIGH IMPEDANCE VDD NOTE: Minimum timing for valid data output. Longer times will initiate an earlier but invalid output. FIGURE 1. READ CYCLE WAVEFORMS AND TIMING DIAGRAM FIGURE 2. MEMORY CELL CONFIGURATION 6-21 DATA OUT DATA IN tDOA1 (NOTE 1) CDP1822C/3 Write Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF LIMITS +25oC, -55oC PARAMETER Write Cycle (Note 1) Address Setup (Note 1) Address Hold (Note 1) Write Pulse Width (Note 1) Data in Setup (Note 1) Data in Hold (Note 1) Chip Select 1 Setup Chip Select 2 Setup Output Disable Setup NOTE: 1. Limits designate 100% testing. All other limits are designer's parameters under given test conditions and do not represent 100% testing SYMBOL tWC tAS tAH tWRW tDIS tDIH tCSS1 tCSS2 tODS VDD (V) 5 5 5 5 5 5 5 5 5 MIN 400 160 40 200 200 40 200 200 140 MAX +125oC MIN 560 225 55 280 280 55 280 280 225 MAX UNITS ns ns ns ns ns ns ns ns ns tWC tAH A0 - A7 tCSSI CHIP-SELECT 1 tCSIH CHIP-SELECT 2 tCSS2 OUTPUT DISABLE (NOTE 1) tODS tCS2H tDIS DATA IN STABLE tWRW tDIH DI1 - DI4 READ/WRITE tAS DON'T CARE NOTE 1 NOTE: 1. tODS is required for common I/O operation only; for separate I/O operations, output disable is don't care. FIGURE 3. WRITE CYCLE TIMING WAVEFORMS 6-22 CDP1822C/3 Data Retention Specifications TEST CONDITIONS +25oC, -55oC PARAMETER Minimum Data Retention Voltage (Note 1) Data Retention Quiescent Current (Note 1) Chip Deselect to Data Retention Time SYMBOL VDR IDD tCDR VDR (V) VDD (V) MIN MAX 2 LIMITS +125oC MIN MAX 2.5 UNITS V A ns 2 - - 70 - 380 - 5 10 5 450 - 650 - Recovery to Normal Operation Time NOTE: tRC 5 450 - 650 - ns 1. Limits designate 100% testing. All other limits are designer's parameters under given test conditions and do not represent 100% testing. VDD tCDR CS2 VIH VIL DATA RETENTION MODE 0.95 VDD tF VDR 0.95 VDD tR tRC VIH VIL FIGURE 4. LOW VDD DATA RETENTION TIMING WAVEFORMS PACKAGE A3 A2 A1 A0 A5 A6 A7 1 2 3 4 5 6 7 8 R VDD 2k A8 A8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 2k R = 2k 20% A8 2k R VDD A1 A8 2k R VDD A0 VDD A4 01 A9 A11 A10 R VDD 01 0 1.6 TEMPERATURE 125oC DURATION 160 Hrs VDD 7V D 2.2 5.0 6.8 7.2 10.0s VDD 0 VDD 0 VDD 0 FIGURE 5. DYNAMIC/OPERATING BURN-IN CIRCUIT AND TIMING DIAGRAM All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 6-23 |
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